This invention relates to a semiconductor memory device with a bit error detecting function for detecting a bit error correction.
As far as we know, there are no RAMs being mass produced and marketed or under development, which can detect a bit error in a semiconductor chip and correct the detected error.
In recent microfabricated semiconductor memory devices, the constituent elements have been remarkably reduced in size, and their package density has been increased. Further, the amount of charge stored as data is minimal. The data stored therein is sensitive to external rays such as .alpha. rays, accordingly. As a result, this creates a serious soft error problem. Thus, bit error due to .alpha. rays, for example, can easily occur in the high package density memory device. If the bit error occurs, it is, of course, necessary to detect and correct it.
A typical conventional detecting and correcting system of one bit error will be given in brief, referring to FIG. 1. In the figure, a plurality of memory cells 1, each for storing one bit, are arrayed in a vertical (Y) direction and a horizontal (X) direction into a matrix memory cell array 2. In addition to the memory cell array 2, a first parity memory circuit 4 is provided, which consists of a plurality of parity storage cells 3 for storing parity bits for the horizontally arrayed memory cells of the memory cell array 2. A second parity memory circuit 6 is further provided, which consists of a plurality of parity storage cells 5 for storing parity bits for the vertically arrayed memory cells of the memory cell array 2.
With such an arrangement, for storing data into the memory cells 1 of the memory cell array 2, parity bits are successively obtained for the data of all of the memory cells 1 of the memory cell array 2, row by row. The parity bits obtained are respectively stored into the corresponding parity storage cells 3 of the first parity memory circuit 4. Similarly, the parity bits of all of the data in the memory cells 1 arrayed of the memory cell array 2 are obtained column by column. The parity bits obtained are respectively stored into the corresponding parity storage cells 5 of the second parity memory circuit 6.
For reading out data from the memory cells 1 of the memory cell array 2, the parity bits in the corresponding parity storage cells 3 of the first parity memory circuit 4 are read out. The parity bit preset in the parity storage cell 5 in the second parity memory circuit 6 is read out. Then, the data read out from the memory cell 1 is parity-checked using the parity bits readout. Namely, it is checked as to whether or not an error is contained in the readout data. When a data error is detected, it is decided that a bit error has occurred, and the data readout of the erroneous memory cells 1 is level-inverted and corrected.
As another known method for detecting and correcting a bit error of up to two bits, an address computer is used.
The memory device shown in FIG. 1 can correct the bit error of only one bit. Further, it requires data-readout bit lines for receiving data read out from the memory cells 1; one for vertical and the other for horizontal. Thus, additional bit lines for the vertical or horizontal must be provided in a design of a general type of semiconductor memory device in which word lines are provided in one direction, and bit lines only in the other direction. This conventional memory device makes the manufacturing process more complicated.
In the case of the bit error detecting/correcting method using the address computer, when it is applied to the semiconductor memory device, a design of the memory device to be employed is quite different from that of the conventional one which causes great difficulty. Further, it is necessary to compute the addresses in the semiconductor memory chip, consuming a long period of time.